The invention relates generally to the electrical, electronic and computer arts, and more particularly relates to a storage controller and method for managing a solid-state memory.
In NAND flash-based solid-state disks (SSDs), data is organized in pages of typically 4, 8, or 16 KB sizes. Page read operations are typically one order of magnitude faster than write operations and latency neither depends on the current nor the previous location of operations. However, memory locations must be erased prior to writing to them. The size of an erase block unit is typically 256 pages and the erase operations takes approximately one order of magnitude more time than a page program operation. Due to these intrinsic properties of the NAND flash technology, SSDs have to write data out-of-place, requiring SSDs to maintain a mapping table that maps logical addresses (e.g., logical block addressing (LBA)) to physical addresses (e.g., physical block addressing (PBA)) called logical-to-physical table (LPT).
As flash chips, blocks and/or pages might expose errors or completely fail due to limited endurance or other reasons, additional redundancy has to be used within flash pages, for example using error correction codes (ECC) and the like, such as Bose-Chaudhuri-Hocquenghem Codes (BCH), as well as across flash chips, for example redundant array of independent disks (RAID)-5 or RAID-6 schemes, or similar. While the addition of ECC in pages is straightforward, the organization of flash blocks into RAID-like stripes is more complex because individual blocks have to be retired over time requiring either reorganizing the stripes or shrinking the capacity of the stripe. As the organization of stripes together with the LPT define the placement of data, SSDs can utilize a so-called log-structured array (LSA) architecture which combines these two methods.
With out-of-place writes, a write operation will write new data to a new location in flash, update the mapping information, effectively invalidating data at the old location. The invalidated data location cannot be reused until the entire block it belongs to has been erased. Before erasing, though, the block has to get garbage-collected, which means, any valid data in the block needs to be relocated to a new block. Garbage collection (GC) of a block is typically deferred for as long as possible to reduce the number of valid pages that must be relocated. Pages that have to be relocated cause additional write operations. The additional write operations constitute write amplification. Since NAND flash has limited endurance, i.e., each cell can only endure a limited number of program and erase cycles, achieving a low write amplification is an important objective. In fact, with shrinking technology nodes in NAND flash, endurance is decreasing dramatically, hence making any sort of write reduction or write elimination even more noticable.
Garbage collection in the context of flash SSD controllers refers broadly to the process of identifying blocks of pages or block-stripes depending on the specific controller and the respective GC unit of operation to be reclaimed for future usage and relocating all remaining valid pages therein. In the following, such a GC unit of operation is referred to as logical erase block (LEB). Note that an LEB may be any multiple of the physical flash block, which is the unit of physical erasure. For instance, in a RAID scheme multiple flash blocks may be grouped together in a block stripe: since the RAID parity is computed against the data in all the participating blocks, these blocks cannot be reclaimed individually. Rather, the full stripe has to be garbage-collected as a single unit. Garbage collecting an LEB entails relocation of any valid logical pages within an LEB to new physical pages to allow for erasing the entire LEB and subsequently make it ready to be populated with new logical pages. The amount of data relocated due to GC relocation of valid pages constitutes garbage collection induced write amplification.
Storage systems based on flash technology are described, for example, in U.S. Patent Application Publication No. 2013/0346725 and U.S. Pat. Nos. 8,880,788 and 8,504,791, the disclosures of which are incorporated by reference herein.